Post on 14-Mar-2021
transcript
EE1411
ElettronicaElettronica AnalogicaAnalogicae e DigitaleDigitale (p(part 1)art 1)
EE1412
Design Abstraction LevelsDesign Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
EE1413
RETI COMBINATORIERETI COMBINATORIE
Algebra booleana: logica binaria (a due stati)
A è una variabile booleana: A=1 oppure A=0
Funzioni logiche elementari per l’algebra Booleana: AND, OR, NOT
EE1414
Logica positiva: livello di tensione + elevatocorrisponde all’1 logico;livello di tensione + bassocorrisponde allo 0 logico;
Logica negativa: livello di tensione + elevatocorrisponde allo 0 logico;livello di tensione + bassocorrisponde all’1 logico.
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PORTE LOGICHEPORTE LOGICHE
La porta NOT.
Out = NOT In1 = In1
In1 Out
01
10
OutIn1
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PORTE LOGICHEPORTE LOGICHELa porta AND.
In1
In2
Out
11 1 01 000 1 00 0
OutIn1 In2Out = In1 AND In2 = In1 • In2
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PORTE LOGICHEPORTE LOGICHELa porta OR.
11 1 11 010 1 00 0
OutIn1 In2Out = In1 OR In2 = In1 + In2
OutIn1
In2
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PORTE LOGICHEPORTE LOGICHELa porta NAND.
01 1 11 010 1 10 0
OutIn1 In2
In1
In2Out
Out = In1 NAND In2 = In1 • In2
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PORTE LOGICHEPORTE LOGICHELa porta NOR.
01 1 01 000 1 10 0
OutIn1 In2
OutIn1
In2
Out = In1 NOR In2 = In1 + In2
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PORTE LOGICHEPORTE LOGICHELa porta XOR.
01 1 11 010 1 00 0
OutIn1 In2
OutIn1
In2
Out=In1 XOR In2=In1·In2+ In1·In2=In1⊕In2
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PORTE LOGICHEPORTE LOGICHELa porta XNOR.
11 1 01 000 1 10 0
OutIn1 In2
OutIn1
In2
Out=In1 XNOR In2=In1·In2+ In1·In2=In1⊕In2
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PROPRIETAPROPRIETA’’ FONDAMENTALIFONDAMENTALI
A+0=AA+1=1A+A=AA+A=1
A • 0=0A • 1=AA • A=AA • A=0
A + A=1A • A=0
A=A
NOT AND OR
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LEGGI DI DE MORGANLEGGI DI DE MORGAN
⋅⋅⋅+++=⋅⋅⋅⋅⋅ CBACBA
⋅⋅⋅⋅⋅=⋅⋅⋅+++ CBACBA
EE14114
Inverter Voltage Transfer CharacteristicInverter Voltage Transfer Characteristic
V(x)
V(y)
V OH
V OL
VM
V OHV OL
fV(y)=V(x)
Switching Threshold
Nominal Voltage Levels
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Mapping logic levels to the voltage domainMapping logic levels to the voltage domain
V IL V IH V in
Slope = -1
Slope = -1
V OL
V OH
Vout
“ 0” VOL
VIL
VIH
VOH
UndefinedRegion
“ 1”
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Definition of Noise MarginsDefinition of Noise Margins
Noise margin high
Noise margin low
VIH
VIL
UndefinedRegion
"1"
"0"
VOH
VOL
NMH
NML
Gate Output Gate Input
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Regenerative PropertyRegenerative Property
A chain of inverters
v0 v1 v2 v3 v4 v5 v6
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v0
v1
v3
finv(v)
f (v)
v3
out
v2 in
Non-RegenerativeRegenerativev2
v1
f (v)
finv(v)
v3
out
v0 inv
v v
vv0
v1
v3
finv(v)
f (v)
v3
out
v2 in
Non-Regenerativev0
v1
v3
finv(v)
f (v)
v3
out
v2 in
Non-RegenerativeRegenerativev2
v1
f (v)
finv(v)
v3
out
v0 in
Regenerativev2
v1
f (v)
finv(v)
v3
out
v0 inv
v v
v
EE14119
2
V (V
olt)
4
v0
v1v2
t (nsec)0
2 1
1
3
5
6 8 10-
EE14120
FanFan--in and Fanin and Fan--outout
N
Fan-out N Fan-in M
M
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The Ideal GateThe Ideal Gate
Ri = ∞Ro = 0Fanout = ∞NMH = NML = VDD/2g = ∞
V in
V out
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An OldAn Old--time Invertertime Inverter
NM H
V in (V)
V
o u t
( V )
NM L
V M
0.0
1.0
2.0
3.0
4.0
5.0
1.0 2.0 3.0 4.0 5.0
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Delay DefinitionsDelay Definitions
Vout
tf
tpHL tpLH
trt
Vin
t
90%
10%
50%
50%
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A FirstA First--Order RC NetworkOrder RC Network
vout
vin C
R
tp = ln (2) τ = 0.69 RC
Important model – matches delay of inverter
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Power DissipationPower Dissipation
Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)
Peak power: Ppeak = Vsupplyipeak
Average power:
( )∫ ∫+ +
==Tt
tTt
t supplysupply
ave dttiT
Vdttp
TP )(1
EE14126
Energy and EnergyEnergy and Energy--DelayDelay
Power-Delay Product (PDP) =
E = Energy per operation = Pav × tp
Energy-Delay Product (EDP) =
quality metric of gate = E × tp
EE14127
A FirstA First--Order RC NetworkOrder RC Network
E0 1→ P t( )dt
0
T
∫ Vdd isupply t( )dt
0
T
∫ Vdd CLdVout0
Vdd
∫ CL Vdd• 2= = = =
Ecap Pcap t( )dt
0
T
∫ Vouticap t( )dt
0
T
∫ CLVoutdVout0
Vdd
∫12---C
LVdd• 2= = = =
vout
vin CL
R