Interconnection of a 3D front-end chip to edgeless/slim-edge and CMOS sensors with advanced

techniquesL. RattiUniversità degli Studi di Pavia and INFN Pavia

OUTLINE

for the IPHC-IRFU / INFN collaboration

Overview of the project

2nd Annual Meeting10-12 April 2013, INFN-LNF, Frascati,

Italy

Status of sensor and readout chip design

Progress with the T-Micro vertical integration process

Test of 3D prototypes

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

Design and fabrication of a multi-tier pixel sensor resulting from the vertical interconnection of a readout chip and of a sensing layer

Goal of the project

CMOS readout chip, based on a 130 nm vertically integrated process (Tezzaron/Globalfoundries)

The project is to be regarded mainly as R&D, although the proposed device is aimed for applications to experiments at the next generation colliders – SuperB, HL-LHC

CMOS sensing layer (XFAB, 350 nm, or an alternative process in 180 nm)

edgeless (or 3D slim edge) fully depleted, planar silicon detector (from FBK, Trento)

vertical interconnection process (m-bumps by T-Micro)

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“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

Tezzaron vertical integration (3D) technology

WB/BB pad

2nd w

afe

r1

st w

afe

r

TSV

Inter-tier bond pads

In wafer-level, three-dimensional processes, multiple strata of planar devices are stacked and interconnected using through silicon vias (TSV)

Fabrication of electrically isolated connections through the silicon substrate (TSV formation)

Substrate thinning (below 50 μm)

3D processes rely upon the following enabling technologies

Inter-layer alignment and mechanical/electrical bonding

Tezzaron Semiconductor technology (via middle approach, vias are made between CMOS and BEOL) can be used to vertically integrate two 130 nm CMOS layers specifically processed by Globalfoundries

Globalfoundries provides a 130 nm CMOS process with several different options; chosen one features 1 poly, 6 metal layers, 2 top metals, dual gate (core and thick oxide devices, 3.3 V), N- and PMOS with different Vth

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“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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Superpix1 readout chip

32x128 elements (2 sub-matrices 16x128), 3.5 x 10 mm2 chip area

ApselVI, DNW MAPS matrix with fast sparsified readout

128x96 pixels

10x5.2 mm2

Superpix1, front-end for hybrid pixels

128x32 pixels

10x3.5 mm2

DNW MAPS

3.25x2 mm2

Hybrid pixelssingle MOS3.25x2 mm2The readout block is designed to

sustain 100 MHz/cm2 hit rate and 100 ns resolution

Data are sent to 4 sparsifiers, each managing 32 rows (corresponding to 8 zones, Wzone=4 pixels)

VHDL simulation of the digital readout block, together with a functional description of the cell matrix, is in progress – P&R to be performed soon

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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Superpix1 analog front-end

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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Superpix1 analog front-end: cell layout

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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High resistivity edge sensors

Planar, p-on-n pixel detectors to be vertically integrated with Superpix1 have been fabricated and are under test – vertical integration with T-Micro (also compatible with IZM process)

Process test structures

Process test structures

128x128

32x128

222x128

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Characterization of prototype active edge sensors is in progress; new sensors to be designed after some feedback from the tests; fabrication to start after FBK clean room re-opening (6-inch process)

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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1st wafer

metal+ oxide

+2nd wafer

Test structures from the 3DIC consortium run

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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3D DNW MAPS: readout functionality tests

Full functionality of vertically integrated chip demonstrated

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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3D DNW MAPS: analog front-end characterization

• Charge sensitivity: 250 mV/fC

• Input dynamic range: 1500 electrons

• ENC: 40 electrons rms

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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3D CMOS process: radiation hardness tests

Single NMOS and PMOS transistors fabricated with the Tezzaron/Globalfoundries process

Irradiated with gamma-rays form a 60Co source (up to 50 Mrad)

Also DNW MAPS have been irradiated and tested

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

Vertical integration with T-Micro

Very high interconnect density, with small bond pads (squares with a side of 5 or 10 μm, depending on the bump size, 2x2 μm2 or 8x8 μm2) both on the sensor and the readout sides more room for top metal routing, in particular for power and ground lines, smaller capacitive coupling, less material

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“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

Alignment rules

Markers for rough and fine alignment (through IR imaging) - apparently not mandatory

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“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

Vertically integrated layers

Preliminary test of the T-Micro integration process performed on pre-existing readout chips (Superpix0) and high resistivity n-on-n pixel sensors (VPix1)

Sensors in the red box have no metal layers under the markers

Front-end chips and a pixel sensor wafer shipped to T-Micro in Dec. 2012

Superpix0 chip layout

6 vertically integrated chips have been shipped back to Italy, tests are in progress

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“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

Surface inspection and alignment

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“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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Conclusion

Design of the front-end chip is progressing quickly, chip design completion is expected for end of June – submission date not set yet, but October might be the right time

Recent results from the characterization of 3D DNW MAPS demonstrated that vertical integration performed by Tezzaron and Ziptronix works – new samples vertically integrated by Tezzaron to be tested soon

Tests on chips vertically integrated by T-Micro (Superpix0 front-end + Vpix pixel sensor) are in progress

Backup slides

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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Item Funding Agency Resources

CMOS sensors(XFAB, 350 nm CMOS)

CNRS 80 kEuro

Edgeless sensors(FBK, Trento)

INFN(VIPIX experiment)

20 kEuro

Slim edge 3D sensors(FBK, Trento)

INFN(TRIDEAS experiment)

33 kEuro

Readout chip(T/G, 3D 130 nm CMOS)

INFN(VIPIX experiment)

125 kEuro

Sensor-to-chip vertical integration

(T-Micro)

AIDA WP3 andINFN (VIPIX experiment)

55 kEuro (INFN) + 145 kEuro (100 kEuro from

CNRS and 45 kEuro from INFN AIDA WP3 budget)

Financial structure of the project

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

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Timescale

Task Delivery time

Edgeless sensor design (FBK) Month 14

Edgeless sensor production (FBK) Month 23

CMOS sensor design (IPHC-IRFU) Month 26

CMOS sensor production (IPHC-IRFU) Month 29

Readout chip design (INFN) Month 17

Readout chip production (INFN) Month 26

Readout chip-to-sensor vertical integration (T-Micro) Month 41

For each task in the table, the delivery time with respect to the AIDA project start date is indicated

“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

~ 2.5 cm

~ 3

.2 c

m

The 3D-IC collaboration

Several groups from US and Europe have been involved in the first 3D MPW for HEP (pixel and strip readout chips for ATLAS, CMS, B-factory, ILC) and photon science applications (X-ray imaging)

Single set of masks used for both tiers to save money

identical wafers produced by Chartered (now Globalfoundries) and face-to-face bonded by Tezzaronbackside metallization by Tezzaron

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“Interconnection of a 3D chip to edgeless and CMOS sensors with advanced techniques”, 2nd AIDA Annual Meeting, 10-12 April 2013

1st wafer

metal+ oxide

+2nd wafersubstrate

DNW MAPS test structures

Small test structures

single pixels with and w/o detector emulating capacitor shunting the readout channel input (analog only)3x3 DNW MAPS matrices (analog only, for charge collection tests)

8x8 and 16x16 DNW MAPS matrices (analog and digital, for readout architecture test)

~ 6.3 mm

~ 5

.2 m

m

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