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Temporizzazioni e sincronismo 1
Progettazione di circuiti e sistemi VLSIProgettazione di circuiti e sistemi VLSI
Anno Accademico 2010-2011
Lezione 10
3.5.2011
Temporizzazioni e sincronizzazione
Temporizzazioni e sincronismo 2
Synchronous Timing
CombinationalLogic
R1 R2Cin Cout Out
In
CLK
tc-q tp,comb
tc-q,cd tcdlog
tsu, thold
Temporizzazioni e sincronismo 3
Latch Parameters
D
Clk
Q
D
Q
Clk
tc-q
thold
PWmtsu
td-q
Delays can be different for rising and falling data transitions
T
tc-q + tp,comb + tsu ≤ T
tc-q,cd + tcdlog > thold
Temporizzazioni e sincronismo 4
Register Parameters
D
Clk
Q
D
Q
Clk
tc-q
thold
T
tsu
Delays can be different for rising and falling data transitions
Temporizzazioni e sincronismo 5
Clock Uncertainties
2
4
3
Power Supply
Interconnect
5 Temperature
6 Capacitive Load
7 Coupling to Adjacent Lines
1 Clock Generation
Devices
Sources of clock uncertainty
Temporizzazioni e sincronismo 6
Clock Nonidealities
• Clock skew– Spatial variation in temporally equivalent clock
edges; deterministic + random, tSK
• Clock jitter– Temporal variations in consecutive edges of the
clock signal; modulation + random noise– Cycle-to-cycle (short-term) tJS
– Long term tJL
• Variation of the pulse width – Important for level sensitive clocking
Temporizzazioni e sincronismo 7
Clock Skew and Jitter
• Both skew and jitter affect the effective cycle time• Only skew affects the race margin
Clk
Clk
tSK
tJS
Temporizzazioni e sincronismo 8
Clock Skew
# of registers
Clk delayInsertion delay
Max Clk skew
Earliest occurrenceof Clk edgeNominal – /2
Latest occurrenceof Clk edge
Nominal + /2
Temporizzazioni e sincronismo 9
Positive and Negative Skew
R1In
(a) Positive skew
CombinationalLogicD Q
tCLK1CLK
delay
tCLK2
R2
D Q CombinationalLogic
tCLK3
R3• • •D Q
delay
R1In
(b) Negative skew
CombinationalLogicD Q
tCLK1
delay
tCLK2
R2
D Q CombinationalLogic
tCLK3
R3• • •D Q
Temporizzazioni e sincronismo 10
Positive Skew
CLK1
CLK2
TCLK
TCLK
th
2
1
4
Launching edge arrives before the receiving edge
Temporizzazioni e sincronismo 11
Negative Skew
CLK1
CLK2
TCLK
TCLK +
2
1
4
3
Receiving edge arrives before the launching edge
Temporizzazioni e sincronismo 12
Timing Constraints
R1
D QCombinational
LogicIn
CLK tCLK1
R2
D Q
tCLK2
tc qtc q, cdtsu, thold
tlogict
Minimum cycle time:T - = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive negative skew)
Temporizzazioni e sincronismo 13
Timing Constraints
R1
D QCombinational
LogicIn
CLK tCLK1
R2
D Q
tCLK2
tc qtc q, cdtsu, thold
tlogict
Hold time constraint:t(c-q, cd) + t(logic, cd) > thold +
Worst case is when receiving edge arrives lateRace between data and clock
Temporizzazioni e sincronismo 14
Impact of Jitter
CLK
-tji tter
TC LK
t j itter
CLK
InCombinat ional
Logic
tc-q , tc-q, cdt log ict log ic, cdtsu, thold
REGS
tjitter
Temporizzazioni e sincronismo 15
Longest Logic Path in Edge-Triggered Systems
Clk
T
tSU
tClk-QTLM
Latest point of launching
Earliest arrivalof next cycle
tJI +
Temporizzazioni e sincronismo 16
Clock Constraints in Edge-Triggered Systems
If launching edge is late and receiving edge is early, the data will not be too late if:
Minimum cycle time is determined by the maximum delays through the logic
tc-q + TLm,cd + tSU < T – tJI,1 – tJI,2 -
tc-q + TLm,cd + tSU + + 2 tJI < T
Skew can be either positive or negative
Temporizzazioni e sincronismo 17
Shortest Path
ClktClk-Q TLm,cd
Earliest point of launching
Data must not arrivebefore this time
ClktH
Nominalclock edge
Temporizzazioni e sincronismo 18
Clock Constraints in Edge-Triggered Systems
Minimum logic delay
If launching edge is early and receiving edge is late:
tc-q,cd + TLm,cd – tJI,1 < tH + tJI,2 +
tc-q,cd+ TLm,cd < tH + 2tJI+
Temporizzazioni e sincronismo 19
How to counter Clock Skew?
RE
G
RE
G
R
EG
.
RE
G
log Out
In
Clock Distribution
Positive Skew
Negative Skew
Data and Clock Routing
Temporizzazioni e sincronismo 20
Latch-Based Design
L1Latch
Logic
Logic
L2Latch
L1 latch is transparentwhen = 0
L2 latch is transparent when = 1
Temporizzazioni e sincronismo 21
Clock Distribution
CLK
Clock is distributed in a tree-like fashion
H-tree
Temporizzazioni e sincronismo 22
The Grid System
D r iv e r
D r iv e r
Dri
ver
Driv
er
G C L K G C L K
G C L K
G C L K
•No rc-matching•Large power
Temporizzazioni e sincronismo 23
Self-timed and Asynchronous Design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Truly asynchronous design
2) Ordering of events is implicit in logic
1) Completion is ensured by careful timing analysis
Self-timed design
1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol